Double patterning is a technology developed for lithography to enhance the feature density. Typically, for forming features of integrated circuits on wafers, lithography technology is used, which involves applying a photo resist, and defining patterns on the photo resist. The patterns in the patterned photo resist are first defined in a lithography mask, and are implemented either by the transparent portions or by the opaque portions in the lithography mask. The patterns in the patterned photo resist are then transferred to the manufactured features.
With the increasing down-scaling of integrated circuits, the optical proximity effect posts an increasingly greater problem. When two separate features are too close to each other, the optical proximity effect may cause the features to short to each other. To solve such a problem, double patterning technology is introduced. The closely located features are separated to two masks of a same double-patterning mask set, with both masks used to expose the same photo resist. In each of the masks, the distances between features are increased over the distances between features in the otherwise a single mask, and hence the optical proximity effect is reduced, or substantially eliminated.
FIG. 1 illustrates a flow of a convention double patterning design. Referring to step 110, a layout of an integrated circuit is determined, and a netlist for the layout is provided. The layout and the netlist are fixed since the sizes and the locations of all of the polygons involved in the layout have been determined. With the fixed layout, the possible back-end-of-line (BEOL) variation, which involves the variations of the metal lines in metal layers, can be estimated (step 112). However, the variations are estimated based on the fixed layout, and hence have fixed values. Next, in step 114, (parasitic) capacitance models are established to simulate the performance value of the integrated circuits, which involves calculating capacitances for metal lines by referring to techfiles. Techfiles may store the capacitances of metal lines as the function of the spacings between metal lines, and as a function of the widths of metal lines.
After the foundary receives the layout design, a layout decomposition is performed to separate the metal lines, for example, according to the double patterning design rules. Lithograph processes are performed to implement the layout on wafers. However, it was found that there was a mismatch between the simulated performance value (step 114) and the performance value measured from the actual wafers. One of the reasons is that when the lithography processes are performed, there may be a relative shift between the two lithography masks of a same double patterning mask. Such shift, however, was not reflected in the estimation of the performance values.